The present invention relates generally to the formation of coplanar interconnectors, and more particularly relates to the field of depositing solder material interconnectors on wafers, substrates, and any other electronic packages requiring solder material microelectronic interconnections.
As used herein the term “interconnector” means a solder-material-deposit attached to an electrical component capable of being electrically interconnected to another electrical component. In addition, the term “microelectronic interconnection” is meant to mean the connection established between two electrical components by one or more interconnectors in a microelectronic package. Finally, the term “solder material” should be understood to include traditional solders as known to those skilled in the art, as well as less traditional materials like lead free solders, polymer based materials, and various other combinations thereof.
Presently, there are a wide variety of microelectronic package interconnections used in modern semiconductor devices. Such microelectronic package interconnections include connections between: IC chips (chip-on-chip stacking), IC chips and carriers, carriers and substrates, and substrates and printed circuit cards. As the need for greater area array densities for microelectronic interconnections increases, improved techniques are developing that allow for solder material to be deposited onto receiving pads contained on wafers and substrates, e.g., bottom layer metallurgy (BLM) and bottom surface metallurgy (BSM).
Related to IC chip and chip carrier interconnections recent developments have been made in flip-chip solder bump technologies in response to increased demand for electrical performance, functionality, and reliability offered by wafer bumping as compared to other technological solutions like wire bonding for example. Using flip-chip technology, solder is deposited on the receiving pads of a wafer in the form of small bumps through the process known as wafer bumping. Unlike wire bonding, wafer bumping allows for area array interconnections across the entire surface of the chip to be deposited with solder bumps that are subsequently microelectronically interconnected to a substrate using a solder reflow process. At the substrate level, solder column connection (SCC) or ceramic column grid array (CCGA) or copper column grid array (CuCGA) technologies have developed providing a process for the attachment of solder columns to the metalicized pads of a substrate (e.g., BSM). Such techniques avoid the disadvantages associated with pin grid array (PGA) interconnections at this level such as higher cost and lower interconnection density.
For CCGA and CuCGA the PbSn (90%/10%), which has melting point greater than 260° C., or copper columns can be joined to a board using PbSn eutectic solder (37%/63%), which has a melting point of 183° C., or lead free solders, which have melting points between 217° C. and 231° C. These structures permit a solder column or copper column to be joined while maintaining a lower joining temperature, for connection to the board, with use of eutectic PbSn solder or lead free solders such as SnAgCu, SnAg, or SnCu. This type of structure also permits a larger height between package and board to be maintained for the solder column and joining solder metallurgy by creating a non-melting solder column and solder melting joining composition for surface attachment to the board. In this multi-solder structure, and for copper column plus solder attachment structures, the resulting product benefits from a longer life prior to fatigue failures of the mounting to a board in reliability testing and in product application for these surface mount attach structures as compared to lower height ball grid array mounting to a board, for similar package sizes.
As the types of interconnectors increases efficient ways for their formation and placement are also being developed. Injection-molded solder (hereinafter “IMS”) technology has been steadily developing in the field of microelectronic interconnections. A discussion of wafer bumping using IMS head technologies is provided by P. A. Gruber, et al., Low-Cost Wafer Bumping, IBM J. Res. & Dev., Vol. 49 No. 4/5 (July/September 2005). IMS has found applicability to flip-chip wafer bumping and CCGA substrate formation. Broadly, IMS wafer bumping is a two-step process in which solder is injected into a mold and subsequently transferred to the surface of a wafer or substrate using a reflow process. The IMS method allows for the controlled injection of molten solder using a variety of mold geometries. Thus the use of IMS has been extended beyond wafer bumping to other microelectronic interconnections, e.g., solder ball and solder column arrays as well as ceramic and organic chip carriers. IMS techniques are further adaptable to the use of a variety of Pb-free solders, including both ternary and quaternary alloys, thus, making the use of IMS more attractive as the microelectronics field moves from PbSn to Pb-free solder and other solder materials.
Even with the developments related to the microelectronic interconnections field, described above, however, significant challenges have yet to be effectively overcome. One of these problems is microelectronic interconnection non-coplanarity. While great pains are taken to create wafers and substrates with planer surfaces variations still remain. The result of depositing solder material interconnectors on non-planar wafers and substrates is non-coplanar interconnectors that negatively impact the resulting microelectronic interconnections. In addition, an efficient means for the creation of coplanar interconnectors that are comprised of more than a single solder material type and/or capable of having various shape geometries has yet to be developed in the field.
A need has therefore been recognized in connection with providing an effective means for achieving coplanar interconnectors and coplanar microelectronic interconnections.